File: genvar_loop_decl_1.ys

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read_verilog -sv genvar_loop_decl_1.sv

select -assert-count 1 gate/genblk1[0].x
select -assert-count 1 gate/genblk1[1].x
select -assert-count 0 gate/genblk1[2].x

select -assert-count 1 gold/genblk1[0].x
select -assert-count 1 gold/genblk1[1].x
select -assert-count 0 gold/genblk1[2].x

proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert