File: wire_and_var.ys

package info (click to toggle)
yosys 0.52-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 69,796 kB
  • sloc: ansic: 696,955; cpp: 239,736; python: 14,617; yacc: 3,529; sh: 2,175; makefile: 1,945; lex: 697; perl: 445; javascript: 323; tcl: 162; vhdl: 115
file content (9 lines) | stat: -rw-r--r-- 412 bytes parent folder | download | duplicates (2)
1
2
3
4
5
6
7
8
9
logger -expect warning "wire '\\wire_1' is assigned in a block" 1
logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1

logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1

logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1
logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1

read_verilog -sv wire_and_var.sv