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Folder: CHAPTER_StateOfTheArt
| .. (parent) | ||||
| - | rw-r--r-- | 215 | always01.v | |
| - | rw-r--r-- | 175 | always01_pub.v | |
| - | rw-r--r-- | 239 | always02.v | |
| - | rw-r--r-- | 195 | always02_pub.v | |
| - | rw-r--r-- | 386 | always03.v | |
| - | rw-r--r-- | 276 | arrays01.v | |
| - | rw-r--r-- | 1,214 | cmp_tbdata.c | |
| - | rw-r--r-- | 261 | forgen01.v | |
| - | rw-r--r-- | 506 | forgen02.v | |
| - | rw-r--r-- | 547 | iverilog-0.8.7-buildfixes.patch | |
| - | rw-r--r-- | 1,518 | mvsis-1.3.6-buildfixes.patch | |
| - | rw-r--r-- | 29,315 | simlib_hana.v | |
| - | rw-r--r-- | 9,767 | simlib_icarus.v | |
| - | rw-r--r-- | 2,981 | simlib_yosys.v | |
| - | rw-r--r-- | 3,135 | sis-1.3.6-buildfixes.patch | |
| - | rwxr-xr-x | 1,811 | synth.sh | |
| - | rwxr-xr-x | 1,216 | validate_tb.sh |
