File: cells_blackbox.v

package info (click to toggle)
yosys 0.8-1
  • links: PTS, VCS
  • area: main
  • in suites: buster
  • size: 9,084 kB
  • sloc: cpp: 82,579; python: 2,725; yacc: 2,018; sh: 1,516; makefile: 884; lex: 492; perl: 399; ansic: 175; vhdl: 46; tcl: 14
file content (18 lines) | stat: -rw-r--r-- 365 bytes parent folder | download | duplicates (4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);

	input wire CE;
	input wire CLK;
	output reg OUT;
	output reg[WIDTH-1:0] POUT;
	input wire RST;
	input wire UP;

	parameter COUNT_TO = 1;
	parameter RESET_MODE = "RISING";
	parameter RESET_TO_MAX = "1";
	parameter HAS_POUT = 0;
	parameter HAS_CE = 0;
	parameter WIDTH = 8;
	parameter DIRECTION = "DOWN";

endmodule